1 ? fn9114.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved. all other trademarks mentioned are the property of their respective owners. ISL6536 four channel supervisory ic the ISL6536 is a four channel supervisory ic designed to monitor voltages >, = 0.7v. this ic bias range is from 2.7v to 4v but can supervise any positive voltage using an external resistor divider to translate to a lower voltage for comparison to the internal 0.63v reference. once properly biased and enabled when all four voltage monitor (vmon) inputs are sa tisfied the pgood output will be immediately released to go high to signal that voltage is valid on all four rails. subsequently when the monitored voltage on any rail drops below its user defined threshold point, the pgood output is pulled low. each rail?s vmon point is independently adjustable with a resistor divider. the pgood output is guaranteed to be valid with ic bias lower than 1v. the vmon inputs will ignore 30s transients on the monitored supplies. the pgood output is an open-drain to allow oring of multiple signals and interfacing to a range of logic levels. the enable input provides for a reset of the pgood output when it is pulled down below 0.5v. with an internal 10ua pull-up to vdd it can be signalled with common logic or pulled to ground with a push button switch. typical application schematic features adjustable undervoltage lockout for each supply active high pgood output guaranteed pgood valid to falling vdd < 1v vmon glitch immunity pb-free available as an option applications graphics cards multi voltage dsps and processors p voltage monitoring embedded control systems intelligent instruments medical equipment network routers portable battery-powered equipment set-top boxes telecommunications systems gnd en 1 2 3 4 8 7 6 5 v1 in v2 in v3 in vmon2 vmon3 vmon1 ISL6536 vmon4 v4 in vdd pgd *opt ordering information part number temp. range (c) package pkg. dwg. # ISL6536ib -40 to +85 8 ld soic m8.15 ISL6536ibz (see note) -40 to +85 8 ld soic (pb-free) m8.15 ISL6536ib-t 8 ld soic tape and reel ISL6536ibz-t (see note) 8 ld soic (pb-free) note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. data sheet may 2004
2 pin descriptions ISL6536 pin name function description 1 vdd bias ic from nominal 2.7v to 4v 2 pgood pgood is the boolean and function of all the uv inputs being satisfied. this is an open drain output and can be pulled high to the appropriate level wi th an external resistor. additionally a 20k ? pull up to vdd is provided internally. 3 enable enabling input for supervisory fu nction. has a 10a pull-up to vdd 4 gnd ic ground 5-8 vmon1 vmon2 vmon3 vmon4 these inputs provide for a programmable monitored vo ltage threshold referenced to an internal 0.63v reference. these inputs have a 30s glitch filter to prevent transient upsets from being recognized by pgood. + - en vmon1 vmon2 vmon3 vmon4 20k 10a vdd pgood ISL6536 633mv falling edge glitch filter ISL6536
3 absolute maximum ratings thermal information vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5v vmon, pgood, enable. . . . . . . . . . . . . . . . . -0.3v to vdd+0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kv (hbm) operating conditions vdd supply voltage range. . . . . . . . . . . . . . . . . . . . . +2.7v to +4v temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . .-40 c to 85 c thermal resistance (typical, note 1) ja ( c/w) 8 ld soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 c maximum storage temperature range . . . . . . . . . . . -65 c to 150 c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 c caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board. see tech brief tb379 f or details. 2. 2. all voltages are relative to gnd, unless otherwise specified. electrical specifications nominal vdd = 3.3v, t a = t j = -40 c - 85 c, unless otherwise specified parameter symbol test conditions min typ max unit bias ic supply current i vdd vmon > vmon _l2h 165 1000 a vdd power on vdd_l2h vdd low to high 2.6 v vdd power on reset vdd_por vdd high to low 2.4 v pgood pull-down current pg pd vpgood = 0.5v 2 ma pull-up resistance pg pu 20 k ? output low v pgl vdd= 1v 0.05 0.1 v delay from vmon rising t pg delvmon last valid input = vth to pg release 2 s delay from en rising t pg delenr en high to pg release 0.05 s delay from en falling t pg delenf en low to pg pulling low 0.015 s enable rising threshold v en enable low to high threshold 0.4vdd 0.5vdd 0.6vdd v threshold hysteresis v en_hys 0.065 v pull-up current i enpu ven = 0.5v 10 a vmon input falling threshold 3.3vmon _h2l tj=+25c 0.623 0.633 0.643 v falling threshold temp coeff. 3.3vmon _tc 100 uv/ c hysteresis vvmon _hys -10-mv range vmon _rng -8-mv glitch filter duration tfil vmon glitch to pgood low filter - 30 - s ISL6536
4 ISL6536 description and operation the ISL6536 is a four channel supervisory ic designed to monitor multiple voltages grea ter than 0.7v. this ic is suitable for both microproce ssors or industrial system applications. upon vdd bias power up the pgood output is held low with vdd as low as 0v. once biased to 2.6v and enabled the ic continuously monitors from one to four voltages independently through external resistor dividers comparing each vmon pin voltage to an internal 0.63v reference. once all vmon input voltages rise above 0.63v the pgood (power good) output signal is released and is pulled high via an external pull resistor to indicate that the power conditions have been met. the pgood output is an open-drain to allow oring of the signals and interfacing to a wide range of logic levels. once any vmon input falls below 0.63v the pgood output is pulled low, the vmon inputs are designed to reject fast transients (30s). if less than four voltages are being monitored, connect the unused vmon pins to vdd. the pgood pin has an internal 20k ? pull-up to vdd making an external pull-up resistor unnecessary. figure 1 illustrates the operational timing diagram. typical performance curves figure 2. vdd current vs. vdd voltage figure 3. vmon threshold vs. vdd voltage figure 1. ISL6536 operational timing diagram vth last en/vmon input pgood output t fil 4/5 en/vmon inputs high vmon _l2h 0.645 0.642 0.639 0.636 0.633 0.627 vmon threshold (v) vdd bias voltage (v) 3.3 2.6 3.9 0.630 3.7 3.5 ISL6536
5 figure 4. en high to pgood figure 5. vmon high to pgood figure 6. en low to pgood figure 7. vmon low to pgood figure 8. en low to pgood figure 9. vmon low to pgood typical performance curves (continued) pg = 1v/div en = 1v/div 1s/div en pgood pg = 2v/div vmon = 1v/div 1s/div pgood vmon en = 1v/div pg = 1v/div 10ns/div en pgood pgood = 2v/div vmon = 1v/div 10s/div vmon pgood en = 1v/div pg = 1v/div 10ns/div en pgood pgood = 2v/div vmon = 1v/div 10s/div vmon pgood ISL6536
6 all intersil u.s. products are manufactured, asse mbled and tested utilizin g iso9000 quality systems. intersil corporation?s quality certifications c an be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL6536 small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93
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